Electronic arrays consist of identical devices arranged in rows and columns. Examples of these arrays include memory clusters, sensor arrays and display panels. The arrays are controlled by address circuits that select or activate (collectively referred to herein as “enable”) the correct rows and columns of elements. These address circuits are usually located in close proximity to the array and have enabling outputs connected to respective row or column lines of the array. Addressing circuits belong to two families of circuits, namely shift registers and decoders. Shift registers allow for the sequential addressing of array lines. Shift registers include logic stages that enable only one of its outputs at a time but also trigger a successive stage. As such, the shift register activates adjacent array lines one after the other, making them suitable for large display or sensor systems. In contrast, decoders are composed of logic stages that require a specific combination of clocks representing a specific address at its input to enable a specific line output.
While shift register circuits tend to require fewer components and therefore occupy less space than decoders, they are prone to multiple stage failures, meaning there is a risk of a stage not being able to trigger the next stage, thereby rendering large blocks of lines useless. This characteristic of shift registers is a significant concern in low yield technologies. Decoders have stages that are independent of each other and failures can be contained to just one line or column. Furthermore, the arrays controlled by decoder circuits can be addressed in a non-sequential manner if desired. This is particularly useful in memory, sensor or display arrays that do not require every line to be enabled during a given cycle. The cost of this improved independence and reliability is found in the size and complexity of decoder structures.
Addressing circuits such as shift registers and decoders are particularly important in large area electronic arrays (such as displays and sensors). These circuits are suitable candidates for integration on the same substrate as the arrays that they control because this integration can reduce the number of interconnections to external components. Applications in this field are restricted for the most part to sensor or display arrays where yield, number of components and area utilization are very important. Shift registers are candidates for addressing these large arrays because of their reduced complexity when compared to decoders. But, because these applications usually extend over a large area, such as a display, it is particularly important to minimize failure regions. As discussed above, arrays controlled by shift registers are subject to consecutive line malfunctions, which severely affect the ability to localize failure regions. For this reason, it may be desirable to implement decoders that would limit potential failures to a single line or column. However, as discussed above, decoder stages necessarily employ complex circuit structures, particularly if the array size is large. This increased complexity affects yield as well as the ability to integrate the decoding structure with the array.
It is desirable, therefore, to provide an addressing architecture with reduced complexity in order to provide high production yield while maintaining the ability to reduce or eliminate successive line failures.